The present invention relates to an improvement to barrel shifters utilizable in, for example, microprocessor data processing. This invention relates more specifically to the speed-up of barrel shifter operations.
Recently, the design of semiconductor integrated circuits (SICs) has become more and more automatized for the reduction of SIC design time. For barrel shifters capable of carrying out any amount of bit shift with a single operation, bit slice structure, i.e., data path architecture having a mask layout that is symmetrical in bits, has been employed widely for a speed-up in the rate of data processing and a reduction in the chip area.
A barrel shifter designed by a conventional data path architecture is now discussed below.
Referring to FIG. 6, a conventional barrel shifter in the data path is illustrated. A register file 20 has a register A and a register B. The register A prestores, as data subjected to bit shift, four bits (i.e., DATA A(3), DATA A(2), DATA A(1), and DATA A(0)). On the other hand, he register B prestores, as signal that designates a bit shift amount, two bits (DATA B(1) and DATA B(0)).
Four flip-flops FFA3, FFA2, FFA1, and FFA0 receive, from the register A, DATA A(3), DATA A(2), DATA A(1), and DATA A(0), respectively. Two flip-flops FFB1 and FFB0 receive, from the register B, DATA B(1) and DATA B(0), respectively. The output value of each flip-flop is updated by a clock signal CLK.
A decode circuit DEC1 decodes an output C1 from the flip-flop FFB1 and provides decode results in the form of a binary bit shift amount at an output terminal C and at an inverting output terminal NC. Likewise, a decode circuit DEC0 decodes an output C0 from the flip-flop FFB0 and provides decode results in the form of a binary bit shift amount at an output terminal C and at an inverting output terminal NC.
21 is a 1-bit shift section. The 1-bit shift section 21 has input terminals D(3), D(2), D(1), and D(0) at which outputs from the flip-flops FFA3, FFA2, FFA1, and FFA0 are input, respectively. 22 is a 2-bit shift section. The 2-bit shift section 22 has input terminals D(3), D(2), D(1), and D(0) at which outputs from output terminals X1(3), X1(2), X1(1), and X1(0) of the 1-bit shift section 21 are input, respectively. The foregoing bit shift amounts of the decode circuits DEC0 and DEC1 control the 1- and 2-bit shift sections 21 and 22, respectively. Based on the bit shift amount received, the 1-bit shift section 21 either shifts each of the data received on the input terminals D(3), D(2), D(1), and D(0) one bit position or carries out no bit shift.
On the other hand, based on the bit shift amount received, the 2-bit shift section 22 either shifts each of the data received on the input terminals D(3), D(2), D(1), and D(0) two bit positions or carries out no bit shift. Outputs at output terminals X2(3), X2(2), X2(1), and X2(0) of the 2-bit shift section 22 are output results of the barrel shifter. In this way, data, output from the register A, are bit-shifted for bit shift amounts represented by the two low-order bits of the register B.
FIG. 7 is a layout of the bit shifter shown in FIG. 6. Referring to FIG. 7, the register file 20, the four flip-flops FFA3, FFA2, FFA1, and FFA0, the 1-bit shift section 21, and the 2-bit shift section 22 are symmetrically laid out in bits in a bit slice structure to form a 4-bit data path.
Referring still to FIG. 7, whereas the decode circuit DEC0 is laid out on the left-hand side of the 1-bit shift section 21, the decode circuit DEC1 is laid out on the left-hand side of the 2-bit shift section 22. Whereas the flip-flop FFB1 is laid out on the left-hand side of the decode circuit DED1, the flip-flop FFB0 is laid out on the left-hand side of the decode circuit DEC0. In other words, the decode circuits DEC0 and DEC1 and the two flip-flops FFB0 and FFB1 are laid out outside the 4-bit data path.
In a barrel shifter designed in accordance with a conventional data path architecture, generally a bit slice structure with a mask layout which is symmetrical in bits includes only the register file 20, the flip-flops FFA3, FFA2, FFA1, and FFA0 that receive data subjected to bit shift, the 1-bit shift section 21, and the 2-bit shift section 22. Both the flip-flops FFB0 and FFB1 that receive data designating a bit shift amount and the decode circuits DEC0 and DED1 are laid out outside the data path. In Japanese Patent Application Publication no. 7-141146, the decode circuits are arranged outside a data path.
However, in the above-described prior art barrel shifter layout structure, both the flip-flops FFB0 and FFB1 that receive bit-shift-amount data and the decode circuits DEC0 and DED1 that decode the bit-shift-amount data are laid out outside the data path. Such arrangement produces the disadvantage that transmission of bit-shift-amount data and bit-shift-amount signals from outside the data path to inside the data path or vice versa is required extra. Proportionally, the rate of barrel shifter operation decreases. For example, in the FIG. 7 layout structure, there is created a great separation between the register file 20 and the two flip-flops FFB0 and FFB1. This results in an increase in the wiring length between the register file 20 and the flip-flops FFB0 and FFB1. This causes a delay in the timing of determining input signals to the flip-flops FFB0 and FFB1, resulting in a drop in the barrel shifter operation rate.